1. Field of the Invention
This invention relates to a charge pump circuit, specifically to a charge pump circuit having charge transfer devices, capacitors that are connected with the charge transfer devices through capacitive coupling and clock drivers that provide the capacitors with clocks.
2. Description of the Related Art
The charge pump circuit boosts a voltage by transferring charges corresponding to the clocks with pumping packets composed of the charge transfer devices such as diodes and the capacitors. The charge pump circuit is widely used as a power supply circuit and the like, and has an advantage over a switching regulator in eliminating a need for a coil as well as reducing a noise. In a charge pump circuit for a power supply to drive a CCD (Charge Coupled Device), for example, a positive voltage booster charge pump circuit and a negative voltage booster charge pump circuit are used since a positive high voltage and a negative high voltage are required.
FIG. 6 is a circuit diagram showing such a kind of charge pump circuit. Diodes D1-D4 are connected in series in a positive booster charge pump circuit 100. A power supply voltage VDD is applied to an anode of a diode D1 in a first stage. A first terminal of each of coupling capacitors C1-C3 is connected to each of connecting nodes between the diodes D1-D4, respectively.
A group of clock drivers 20 provides second terminals of the coupling capacitors C1-C3 with clocks in a way that the second terminals next to each other are provided with the clocks opposite in phase to each other. The group of drivers 20 is composed of first, second and third clock drivers 21, 22 and 23 and first, second and third delay circuits 24, 25 and 26. A clock CLK delayed by the first delay circuit 24 is applied to the second terminal of the coupling capacitor C1 through the first clock driver 21. A clock CLKB delayed by the second delay circuit 25 is applied to the second terminal of the coupling capacitor C2 through the second clock driver 22. The clock CLKB is opposite in phase to the clock CLK. The clock CLK delayed by the third delay circuit 26 is applied to the second terminal of the coupling capacitor C3 through the third clock driver 23.
A positive boosted voltage of 4VDD is obtained from a cathode of the diode D4 in a final stage as a first output voltage Vout1. The effect of threshold voltages of the diodes D1-D4 is neglected. Cout1 denotes a first output capacitor and L1 denotes a first load device to which an output current Iout1 of the first output voltage Vout1 from the positive booster charge pump circuit 100 is supplied.
Diodes D5-D7 are connected in series in a negative booster charge pump circuit 200. A ground voltage VSS (0V) is applied to a cathode of the diode D5 in a first stage. A first terminal of each of coupling capacitors C5 and C6 is connected to each of connecting nodes between the diodes D5-D7, respectively.
A group of clock drivers 30 provides second terminals of the coupling capacitors C5 and C6 with clocks in a way that the second terminals next to each other are provided with the clocks opposite in phase to each other. The group of clock drivers 30 is composed of fourth and fifth clock drivers 31 and 32 and fourth and fifth delay circuits 33 and 34. The clock CLK delayed by the fourth delay circuit 33 is applied to the second terminal of the coupling capacitor C5 through the fourth clock driver 31. The clock CLKB delayed by the fifth delay circuit 34 is applied to the second terminal of the coupling capacitor C6 through the fifth clock driver 32.
A negative boosted voltage of −2VDD is obtained from an anode of the diode D7 in a final stage as a second output voltage Vout2. The effect of threshold voltages of the diodes D5-D7 is neglected. Cout2 denotes a second output capacitor and L2 denotes a second load device to which an output current Iout2 of the second output voltage Vout2 from the negative booster charge pump circuit 200 is supplied.
FIG. 7 is a circuit diagram showing the first clock driver 21 and the first delay circuit 24. The first clock driver 21 is composed of a P-channel type MOS transistor 211 and an N-channel type MOS transistor 212 connected between the power supply voltage VDD and the ground voltage VSS. A connecting node between the P-channel type MOS transistor 211 and the N-channel type MOS transistor 212 makes an output terminal OUT.
The first delay circuit 24 is composed of a first inverter chain 241 made of three inverters connected in series, a second inverter chain 242 and a third inverter chain 243, both of which receive an output of the first inverter chain 241. The power supply voltage VDD and the ground voltage VSS are provided as power supplies to each of inverters constituting these inverter chains.
The clock CLK is supplied to an input terminal IN of the first inverter chain 241. An output of the second inverter chain 242 is applied to a gate of the P-channel type MOS transistor 211, while an output of the third inverter chain 243 is applied to a gate of the N-channel type MOS transistor 212. The second inverter chain 242 is designed so as to output a low level (the ground voltage VSS) slower than the third inverter chain 243. On the other hand, the third inverter chain 243 is designed so as to output a high level (the power supply voltage VDD) slower than the second inverter chain 242. Simultaneous turning on of the P-channel type MOS transistor 211 and the N-channel type MOS transistor 212 of the first clock driver 21 and resulting through-current are prevented from occurring by the design.
The second through fifth clock drivers 22, 23, 31 and 32 and the second through fifth delay circuits 25, 26, 33 and 34 are configured similarly.
The technology mentioned above is disclosed in Japanese Patent Application Publication No. 2001-231249, for example.
Since the first delay circuit 24 operates with the power supply voltage VDD and the ground voltage VSS, however, a voltage between the gate and a source of each of the MOS transistors in the first clock driver 21 when it is turned on is VDD at the most. There arises a problem, especially with the P-channel type MOS transistor 211, that a size of the transistor becomes very large in order to reduce an ON-resistance of the transistor.